1. Field of the Invention
The present invention generally relates to wiring methodologies for electronic packages and more particularly to a method for optimizing the wiring of multiple media wiring packages.
2. Description of the Prior Art
Multi-Chip Modules (MCMs) are becoming increasingly popular as cost effective electronic packages. They have been used in high performance computing for many years, typically in main frame computers; now they are being considered for workstations and personal computers.
There is a trend in the MCM industry to produce packages based on thin film technology. Thin film permits greater density of pins and wiring channels, but is usually expensive. A compromise solution is to use thin film for some of the wiring layers, and a less expensive material, such as ceramic, for the remaining layers. Such packages are usually called hybrid MCMs. In general, packages with more than one wiring medium can be called multiple wiring media packages.
Multiple wiring media packages present new challenges to wiring algorithms and package wiring methodologies. They have several characteristics which need special attention during wiring, including the following:
the different media used for wiring are very different in their wiring geometries and electrical properties; PA1 the interface resources which allow connections to go from one medium to another are very scarce; and PA1 the different electrical properties on different media usually lead to different network models. PA1 maximize the number of networks wired (this is usually the primary objective since completing all networks defined by the logic of the electronic package is a prerequisite to having a complete wiring design); PA1 maximize the utilization of wiring resources (the utilization is represented as a percentage of the total wiring capacity that is populated by wires); PA1 minimize the length of the connections (this leads to better delay performance); and PA1 minimize the electrical noise (this helps assure the proper functioning of the circuits).
For example, resistance must be taken into account in thin film wiring while ceramic wiring must contend with capacitance. These differences mean that certain network topologies which are optimal in ceramic under particular circumstances are not optimal in thin film, and vice versa. Also, ceramic technology requires a wider spacing between pins and fewer wires in wiring channels. This difference in physical scale, coupled with manufacturing limitations for attaching pins to thin film surfaces, significantly reduces the availability of vias between thin film and ceramic layers.
In principle, the characteristics of each medium can be exploited by wiring different types of networks on the different media. However, the prior art discloses no wiring method which effectively integrates the use of multiple network models in a single package composed of multiple media.
Optimizing the wiring of an electronic package is an important step in the design process. A well optimized wiring method helps in reducing the cost of the package, as it leads to a better utilization of the available wiring resources of the package. It also helps in improving the performance characteristics of the package, since smaller wire lengths induce smaller delays in the signal. Several quantities should be optimized during the wiring process, including
The general problem of optimizing wiring connections between multiple electronic elements each having multiple pins has been addressed in the prior art. For example, U.S. Pat. No. 3,702,004 to Eskew et al. describes a technique for optimally interconnecting elements on a printed circuit board through wiring laid out on both sides of the board by constructing a numbered ordered maze from one pin to another and then backtracking to find the shortest path. More broadly, U.S. Pat. No. 4,500,963 to Smith discloses an automatic layout program for optimizing the wiring of hybrid microcircuits ranging from discrete microcircuits to very large scale integrated circuits. The Smith patent discloses a routing technique which uses multiple wiring layers, under a process which proceeds sequentially from top to bottom or bottom to top using two adjacent layers at a time; within each layer pair iteration, a two phased algorithm operates to (a) establish increasing numerical levels for grid points on the routing surface between source and sink points and then (b) find an optimum path back from the sink point to the source point by proceeding toward decreasing numerical levels in accordance with certain priority rules. Numerical levels of intervening points may be weighted to reflect physical design objectives. The priority rules allow connections between levels through "vias" but promote paths which are in alternative orthogonal directions for alternative layers.
Prior art approaches to optimization do not find it necessary to have a separate medium assignment step nor to deal with wiring constraints at the interfaces between media with significantly different electrical and geometric characteristics. The conventional approach is to route one connection at a time, selecting vias as the router proceeds. If this approach is followed for a multiple wiring media package, a very non-optimal solution will result, as the interface vias will be utilized in a very non-optimal fashion.
For more background related to the invention to be described below, the reader is referred to the books by Kloman, Bernard, and Robert E. Beck, Elementary Linear Programming with Applications, Academic Press (1980), Lengauer, Thomas, Combinational Algorithms for Integrated Circuit Layout, John Wiley and Sons (1990), and Preas, Bryan T., and Michael J. Lorenzetti, Editors, Physical Design Automation of VLSI Systems, The Benjamin/Cummings Publishing Co., Inc. (1988), and the article by Ralph Linsker, entitled "An iterative-improvement penalty-function-driven wire routing system", IBM Journal of Research and Development, Vol. 28, No. 5, September 1984, pp. 613-624, all of which are incorporated herein by reference.